`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/06 19:24:01
// Design Name: 
// Module Name: tb_syc_fifo
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_syc_fifo;

reg clock;
reg rst_n;
reg wren;
reg [31:0] wrdata;
reg rden;
wire [31:0] rdata;
wire full;
wire empty;
reg [31:0] test_data;

initial begin
    clock = 0;
    forever begin
        #5 clock = ~clock;
    end
end

initial begin
    rst_n = 0;
    #20 rst_n = 1;
end

//initial begin
//    wren = 0;
//    wrdata = 0;
//    test_data = 0;
//    #30;
//    repeat(10) begin
//        @(negedge clock) begin
//            wren = 1;
//            test_data = test_data + 1;
//            wrdata = test_data;
//        end
//        repeat(15) begin
//            @(negedge clock) begin
//                wren = 0;
//            end
//        end
//    end
//end

//initial begin
//    rden = 0;
//    #40;
//    repeat(10) begin
//        @(negedge clock) begin
//            rden = 1;
//        end
//        repeat(21) begin
//            @(negedge clock) begin
//                rden = 0;
//            end
//        end
//    end
//end



initial begin
    wren = 0;
    wrdata = 0;
    test_data = 0;
    #30;
    repeat(10) begin
        @(posedge clock) begin
            wren = 1;
            test_data = test_data + 1;
            wrdata = test_data;
        end
        repeat(15) begin
            @(posedge clock) begin
                wren = 0;
            end
        end
    end
end

initial begin
    rden = 0;
    #40;
    repeat(10) begin
        @(posedge clock) begin
            rden = 1;
        end
        repeat(21) begin
            @(posedge clock) begin
                rden = 0;
            end
        end
    end
end

initial begin
#2050
$finish;
end

SYC_FIFO #(.FIFO_WIDTH(32)) FIFO_0(
    .fifo_clk(clock),
    .fifo_rst_n(rst_n),
    .fifo_wren(wren),
    .fifo_wrdata(wrdata),
    .fifo_rden(rden),
    .fifo_rdata(rdata),
    .fifo_full(full),
    .fifo_empty(empty)
);


endmodule
